1. Field of the Invention
The present invention generally relates to a data processing system, and more particularly relates to a bi-polar integrated circuit semiconductor chip forming a memory-sense amplifier and memory-bus driver.
2. Description of Prior Art
The prior art includes examples of integrated circuit construction of computer memories, amplifiers, and central processing units (CPU's). The technologies that are employed for these constructions include MOS (metal oxide semiconductor) and bi-polar technologies. For example, semiconductor memories such as those termed random access memories (RAMs), read only memories (ROMs), and programmable read only memories (PROMs), if constructed from MOS technology, may each be fabricated on a single silicon substrate.
In semiconductor MOS, memory cells are either static or dynamic. The static type of cell generally includes bi-stable circuits such as flip-flops which once set in a particular state remain in that state without periodic re-energization or "refreshing". But, static circuits require a relatively large number of devices, for example, several field effect transistors are required to make a flip-flop. By comparison the dynamic memory cells typically employ capacitor storage and thus require fewer devices to store a bit of information, but since such storage is transient, refreshing of the information stored on the inherent capacitance is required periodically.
The size of a memory array which may be fabricated on a semiconductor chip is limited by the number of electrical connections made to a given size LSI (large scale integrated circuit) chip, and the quantity of semiconductor devices formed on the chip. In accordance with known probability factors effecting LSI fabrication techniques, production yield of LSI chips is inversely related to the area of the chip, which determines the number of semiconductor devices on the chip, so that an increase in the chip size and consequently the number of semiconductors thereon would tend to decrease its production yield. Therefore, with the given size LSI chip, increases in the size of a memory array on the chip can be most practically achieved by decreasing the number of semiconductor devices required to store a binary digit, for example, by using capacitive storage memory cells which require fewer semiconductor devices than the more conventional bi-polar or flip-flop memory cell. The main memory of the present invention is thus constructed from MOS, or capacitively refreshed memory cells, to obtain the reduced area/increased yield advantages, and others as well.
Having chosen MOS fabrication for the memories of the data processing system in which the present invention is employed, a discussion of the background of sense-amplifiers is now in order. Sense amplifiers as referred to in combination with MOS memory structure fall into two basic categories. The first category is memory cell state sensing, as exemplified by two prior art patents: U.S. Pat. Nos. 3,967,252 and 4,003,034.
The second category is memory state level conversion, (also known to those skilled in the art as "sensing", which may tend to cause some ambiguity). One technique presently used in this second category is conversion from MOS voltage levels to higher Bi-polar voltage levels using some of the MOS circuitry of the very chip for which the levels are being converted; this technique requires external buffering, as, for example, by a TTL buffer, in order to drive memory busses. Another technique presently used in this second category is level conversion from MOS levels to bi-polar levels external of the MOS chip, this other technique being related to operation of the present invention.
More specifically, the first technique for level shifting is a common design approach which had been used and which is presently still employed, and which is to fabricate on a single chip, an MOS memory chip and an MOS level converter. The level conversion is needed in order to make the MOS voltage levels compatible with higher TTL or bi-polar voltage levels, the TTL circuitry being employed normally in bus driver circuits, since more current is available with TTL than with MOS. One of the shortcomings of this first technique, however, is that relatively large propagation delays are inherently associated with level shifting as accomplished by MOS technology, due, at least in part, to the inherent capacitance involved.
As noted above, Applicant's invention operates with the other level conversion technique, and which thus enables a solution to this time propagation shortcoming by not requiring level shifting with MOS circuitry. Instead, the MOS memory chip provides its MOS-level output by way of an open collector MOS (or open drain MOSFET) transistor, to a second bi-polar chip, and thus presents an output having a variation in impedance rather than a variation in voltage level. The second bi-polar chip forms sense amp/bus driver circuitry, which circuitry senses the impedance level variation from the MOS memory chip, utilizing novel circuitry, and thus solves the above noted prior art problem. The impedance level variation associated with an open-drain MOSFET can typically be from 100 kilohms to 2 kilohms.
Other problems affecting sense amplifier or level converter operation, that have existed in the prior art include those derived from deleterious external effects on operation of the integrated circuit (IC) chip, e.g., external power supply variations. External effects were derived, in part, from the fact that the prior art sense amplifiers were not self-contained; off-chip, discrete components were used to generate reference and clamping levels. Therefore variations in the power supply including those variations that may have had a dis-proportionate impact, either on the integrated circuit or the discrete components, would create circuit operational problems. Variations in power supply level can create excessive delays, instabilities, and eventual malfunctions.
Additional delays can be created by not clamping or controlling switching voltage levels within specific limits. Clamping of voltages within specific tolerances can be accomplished by certain techniques that are suitable for implementation by bi-polar methods. One of these clamping techniques employs cascoded transistors to limit voltage swings, as for example those in a switching differential amplifier. In the prior art, this kind of cascoded collector-voltage variation-limit was of necessity fabricated from either multiple-chip bi-polar integrated circuits, or from hybrid discrete component/IC combinations. This swing-limit circuit was therefore accompanied by inherent drawbacks associated with either having discretes or with having more than one chip performing the amplification function. The present invention provides a solution to these other problems, as well.
The present invention employs a unique reference voltage generation and biasing scheme which makes the circuitry relatively insensitive to power supply variation, thereby obviating problems derived therefrom, and further permits construction of this reference voltage generation/biasing circuitry, and voltage swing limiting circuitry on a single chip, thereby obviating multiple chip and off-chip discrete component problems as well.